Embodiments disclosed in the present invention relate generally to electrical technology, and more specifically to a semiconductor component and method of fabricating the same.
Semiconductor devices providing a bi-directional circuit by the use of a pair of transistors sharing a common drain have become more desirable since the common drain connected transistors allow more efficient current conduction in a monolithic integrated circuit. However, due to the configuration of transistors and the vertical current conduction, a region of reduced electric current density is observed. The current density can be improved by arranging the source regions to have greater uniformity across the entirety of the device. In addition, for the dual common drain architecture, the major cause of source-to-source on-resistance are the main device resistance, the substrate resistance, and back metal resistance, primarily due to lateral current flow from one source to the other. In the past, attempts to reduce this resistance included one or all of the following: (i) thinner substrate and thicker back metal, (ii) lower resistivity back metal, and/or (iii) reduced distance from the first to the second source areas. However, some of these methods to reduce the on-resistance present challenges; for example, by producing a thinner wafer, the risk of wafer cracking increases as the wafer thickness decreases. The previous devices also have a back metal, which increases the cost of the device.
Accordingly, it would be desirable to have a common drain semiconductor device structure that has a lower source-to-source on-resistance and greater uniformity to produce increased electrical current density, without the need for a thinner wafer. It would also be desirable to decrease the cost of the device by omitting the back metal.
For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote generally the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. It will be appreciated by those skilled in the art that the words “during”, “while”, and “when” as used herein relating to circuit operation are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as propagation delay, between the reaction that it initiated by the initial action. Additionally, the term “while” means that a certain action occurs at least with some portion of duration of the initiating action. The use of the word “approximately” or “substantially” means that a value of an element has a parameter that is expected to be close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the value or positions from being exactly as stated. It is well established in the art that variances of up to at least 10 percent (10%) are reasonable variances from the ideal goal of exactly as described. The terms “first”, “second”, “third” and the like in the Claims and/or in the Detailed Description of Drawings, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments described herein are capable of operation in other sequences than described or illustrated herein. For clarity of the drawings, doped regions of device structures are illustrated as having generally straight line edges and precise angular corner. However, those skilled in the art understand that due to the diffusion and activation of dopants, the edges of doped regions generally may not be straight lines and the corners may not be precise angles.